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w39l040a data sheet 512k 8 cmos flash memory publication release date:april 14, 2005 - 1 - revision a3 table of contents- 1. general description ......................................................................................................... 3 2. features ................................................................................................................................. 3 3. pin configurations ............................................................................................................ 4 4. block diagram ...................................................................................................................... 4 5. pin description ..................................................................................................................... 4 6. functional description ................................................................................................... 5 6.1 device bus operation ..................................................................................................... 5 6.1.1 read mode .......................................................................................................................5 6.1.2 write mode .......................................................................................................................5 6.1.3 standby mode ..................................................................................................................5 6.1.4 output disable mode ........................................................................................................5 6.1.5 auto-select mode ..............................................................................................................5 6.2 data protection ............................................................................................................... 6 6.2.1 low vdd inhibit ................................................................................................................6 6.2.2 write pulse "glitch" protection .........................................................................................6 6.2.3 logical inhibit ...................................................................................................................6 6.2.4 power-up write and read inhibit ......................................................................................6 6.3 command definitions ..................................................................................................... 6 6.3.1 read command ...............................................................................................................6 6.3.2 auto-select command ......................................................................................................7 6.3.3 byte program command ..................................................................................................7 6.3.4 chip erase command ......................................................................................................7 6.3.5 sector erase command ...................................................................................................8 6.4 write operation status ................................................................................................... 8 6.4.1 dq7: #data polling ...........................................................................................................8 6.4.2 dq6: toggle bit ................................................................................................................9 6.5 table of operating modes .............................................................................................. 9 6.5.1 device bus operations .....................................................................................................9 6.5.2 auto-select codes (high voltage method) .......................................................................9 6.5.3 sector address table .....................................................................................................10 6.5.4 command definitions .....................................................................................................10 6.6 embedded programming algorithm ............................................................................. 11 6.7 embedded erase algorithm .......................................................................................... 12
w39l040a - 2 - 6.8 embedded #data polling algorithm .............................................................................. 13 6.9 embedded toggle bit algorithm ................................................................................... 13 7. electrical characteristics ......................................................................................... 14 7.1 absolute maximum ratings .......................................................................................... 14 7.2 dc operating characteristics ....................................................................................... 14 7.3 pin capacitance ............................................................................................................ 14 7.4 ac characteristics ........................................................................................................ 15 7.4.1 ac test conditions .........................................................................................................15 7.4.2 ac test load and waveform .........................................................................................15 7.4.3 read cycle timing parameters ......................................................................................16 7.4.4 erase/program cycle timing parameters ......................................................................16 7.4.5 power-up timing ............................................................................................................17 7.4.6 #data polling and toggle bit timing parameters ...........................................................17 8. timing waveforms ............................................................................................................. 18 8.1 read cycle timing diagram ......................................................................................... 18 8.2 #we controlled command write cycle timing diagram ............................................. 18 8.3 #ce controlled command write cycle timing diagram .............................................. 19 8.4 chip erase timing diagram ......................................................................................... 19 8.5 sector erase timing diagram ...................................................................................... 20 8.6 #data polling timing diagram ...................................................................................... 20 8.7 toggle bit timing diagram ........................................................................................... 21 9. ordering information .................................................................................................... 22 10. how to read the top marking ...................................................................................... 23 11. package dimensions ......................................................................................................... 24 11.1 32l plcc ..................................................................................................................... 24 11.2 32l pdip ....................................................................................................................... 24 11.3 32l tsop (8 x 20 mm) ................................................................................................. 25 11.4 32l stsop (8 x 14 mm) .............................................................................................. 25 12. version history ................................................................................................................. 26
w39l040a publication release date: april 14, 2005 - 3 - revision a3 1. general description the w39l040a is a 4mbit, 3v/3.3v cmos flash memory organized as 512k 8 bits. for flexible erase capability, the 4mbits of data are divided into 8 uniform sectors of 64 kbytes. the byte-wide ( 8) data appears on dq7 ? dq0. the device can be programmed and erased in-system with a standard 3.3v power supply. a 12-volt v pp is not required. the unique cell architecture of the w39l040a results in fast program/erase operati ons with extremely low current consumption (compared to other comparable 3.3-volt flash memo ry products). the device can also be programmed and erased by using standard eprom programmers. 2. features ? 3v/3.3-volt read/erase/program operations ? 3.0 ~ 3.6v for 70ns ? 2.7 ~ 3.6v for 90ns ? fast program operation: ? byte-by-byte programming: 9 s (typ.) ? fast erase operation: ? chip erase cycle time: 6 s (typ.) ? sector erase cycle time: 0.7 s (typ.) ? read access time: 70/90 ns ? 8 even sectors with 64k bytes ? any individual sector can be erased ? typical program/erase cycles: 10k ? twenty-year data retention ? low power consumption ? active read current: 7 ma at 5mhz (typ.) ? active program/erase current: 15 ma at 5mhz (typ.) ? standby current: 0.2 a (typ.) ? end of program detection ? software method: toggle bit/#data polling ? jedec standard byte-wide pinouts ? available packages: 32-pin plcc lead free, 32-pin stsop (8 x 14 mm) lead free, 32-pin pdip and 32-pin tsop (8 x 20 mm)
w39l040a - 4 - 3. pin configurations 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 3031 32 1 2 3 4 8 2019 18171615 14 d q 1 d q 2 d q 3 d q 4 d q 5 d q 6 a14 a13 a8 a9 a11 #oe a10 #ce dq7 a 1 2 a 1 6 v d d # w e a 1 5 a 1 7 32l plcc v s s a 1 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a3 a2 a1 a0 dq0 dq1 dq2 v #oe a10 #ce dq7 dq6 dq5 dq4 dq3 32l stsop and 32l tsop a15 a12 a7 a6 a5 a4 v #we a14 a13 a8 dd a11 a9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 a17 ss a18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq0 dq1 dq2 vss a7 a6 a5 a4 a3 a2 a1 a0 a16 a15 a12 v #we a14 a13 a8 a9 a11 #oe a10 #ce dq7 dq6 dq5 dq4 dq3 dd a17 32-pin dip a18 4. block diagram control output buffer decoder core array #ce #oe #we a0 . . a18 . . dq0 dq7 v dd v ss 5. pin description symbol pin name a0 ? a18 address inputs dq0 ? dq7 data inputs/outputs #ce chip enable #oe output enable #we write enable v dd power supply v ss ground
w39l040a publication release date: april 14, 2005 - 5 - revision a3 6. functional description 6.1 device bus operation 6.1.1 read mode the read operation of the w39l040a is controlled by #ce and #oe, both of which have to be low for the host to obtain data from the outputs. #ce is used for device selection. when #ce is high, the chip is de-selected and only standby power will be consum ed. #oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either #ce or #oe is high. refer to the timing waveforms for further details. 6.1.2 write mode device erasure and programming are accomplished vi a the command register. the contents of the register serve as inputs to the in ternal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with t he address and data information needed to execute the command. the command register is written by bringing #we to logic low state; while #ce is at logic low state and #oe is at logic hi gh state. addresses are latched on the falling edge of #we or #ce, whichever happens later; while data is latched on the rising edge of #we or #ce, whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/program waveforms for specific timing parameters. 6.1.3 standby mode the standby mode is achieved with the #ce input held at v dd 0.3v and the current is typically reduced to less than 5 a (max). in the standby mode the outputs are in the high impedance state, independent of the #oe input. 6.1.4 output disable mode with the #oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. 6.1.5 auto-select mode the auto-select mode allows the reading of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be progra mmed with its corresponding programming algorithm. this mode is functional over the ent ire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5v to 12.5v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by t oggling address a0 from v il to v ih . all addresses are don t cares except a0 and a1 (see "auto-select codes"). the manufacturer and device codes may also be r ead via the command register, for instance, when the w39l040a is erased or programmed in a system wit hout access to high voltage on the a9 pin. the command sequence is illustrated in "auto-select codes".
w39l040a - 6 - byte 0 (a0 = v il ) represents the manufacturer s code (winbond = dah) and byte 1 (a0 = v ih ) the device identifier code ( w39l040a = d6hex). all identifiers for m anufacturer and device will exhibit odd parity with dq7 defined as the parity bit. in order to read the proper device codes when executing the auto-select, a1 must be low state. 6.2 data protection the w39l040a is designed to offer protection against acci dental erasure or programming caused by spurious system level signals that may exist dur ing power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents onl y occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v dd power-up and power-down transitions or system noise. 6.2.1 low v dd inhibit to avoid initiation of a write cycle during v dd power-up and power-down, the w39l040a locks out when v dd < 2.0v (see dc characteristics section fo r voltages). the write and read operations are inhibited when v dd is less than 2.0v typical. the w39l040a ignores all write and read operations until v dd > 2,0v. the user must ensure that the cont rol pins are in the correct logic state when v dd > 2.0v to prevent unintentional writes. 6.2.2 write pulse "glitch" protection noise pulses of less than 10 ns (typical) on #oe, #ce, or #we will not initiate a write cycle. 6.2.3 logical inhibit writing is inhibited by holding any one of #oe = v il , #ce = v ih , or #we = v ih . to initiate a write cycle #ce and #we must be a logical zero while #oe is a logical one. 6.2.4 power-up write and read inhibit power-up of the device with #we = #ce = v il and #oe = v ih will not accept commands on the rising edge of #we except 5ms delay (see the power up timi ng in ac characteristics). the internal state machine is automatically reset to the read mode on power-up. 6.3 command definitions device operations are selected by writing s pecific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "command definitions " defines the valid register command sequences. 6.3.1 read command the device will automatically power-up in the read state. in this case, a command sequence is not required to read data. standard microprocessor read cycl es will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. the device will automatically returns to r ead state after completing an embedded program or embedded erase algorithm. refer to the ac read characteristics and wave forms for the specific timing parameters.
w39l040a publication release date: april 14, 2005 - 7 - revision a3 6.3.2 auto-select command flash memories are intended for use in applications where the local cpu can alter memory contents. as such, manufacture and device codes must be acce ssible while the device resides in the target system. prom programmers typically access the si gnature codes by raising a9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally a desirable system design practice. the device contains an auto-select command operat ion to supplement traditional prom programming methodology. the operation is initiated by writ ing the auto-select command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of dah. a read cycle fr om address xx01h returns the device code ( w39l040a = d6hex). to terminate the operation, it is necessary to write the auto-select exit command sequence into the register. 6.3.3 byte program command the device is programmed on a byte-by-byte basis. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. the program address and data are wr itten next, which in turn initiate the embedded program algorithm. addresses are latched on t he falling edge of #ce or #we, whichever happens later and the data is latched on the rising edge of #ce or #we, whichever happens first. the rising edge of #ce or #we (whichever happens first) begins programming using the embedded program algorithm. upon executing the algorithm, the system is not required to provide further controls or timings. the device will automatically provide adequat e internally generated program pulses and verify the programmed cell margin. the automatic programming operation is comple ted when the data on dq7 (also used as #data polling) is equivalent to the data written to this bi t at which time the device returns to the read mode and addresses are no longer latched (see "hardwar e sequence flags"). therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for #data polling operations. #data polling must be performed at the memory location which is being programmed. any commands written to the chip during t he embedded program algorithm will be ignored. if a hardware reset occurs during the programming operati on, the data at that particular location will be corrupted. programming is allowed in any sequence and across sector boundaries. beware that a data "0" cannot be programmed back to a "1". attempting to program 0 back to 1, the toggle bit will stop toggling. only erase operations can convert "0"s to "1"s. refer to the programming command flow chart using typical command strings and bus operations. 6.3.4 chip erase command chip erase is a six-bus-cycle operation. there are two "unlock" write cycles , followed by writing the "set-up" command. two more "unl ock" write cycles are asserted, followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devic e will automatically erase and verify the entire memory for an all one data pattern. the eras e is performed sequentially on each sectors at the
w39l040a - 8 - same time (see "feature"). the syst em is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last #we pulse in the command sequence and terminates when the data on dq7 is "1" at whic h time the device returns to read the mode. refer to the erase command flow chart using typical command strings and bus operations. 6.3.5 sector erase command sector erase is a six-bus-cycle oper ation. there are two "unlock" writ e cycles, followed by writing the "set-up" command. two more "unlo ck" write cycles then follows by the sector erase command. the sector address (any address location within the des ired sector) is latched on the falling edge of #we, while the command (30h) is latched on the rising edge of #we. sector erase does not require the user to program t he device prior to erase. when erasing a sector or sectors the remaining unselected sectors are not affe cted. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the eras e command is completed, right from the rising edge of the #we pulse for the last sector erase command pulse and terminates when the data on dq7, #data polling, is "1" at which time the device returns to the read mode. #data polling must be performed at an address within any of the sectors being erased. refer to the erase command flow chart using typical command strings and bus operations. 6.4 write operation status 6.4.1 dq7: #data polling the w39l040a device features #data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq7. upon completi on of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq7. during the embedded erase algorithm, an attempt to read the device will produce a "0" at the dq7 output. upon completion of the embedded erase algorithm, an attempt to read the device will produce a "1" at the dq7 output. for chip erase, the #data polling is valid after t he rising edge of the sixth pulse in the six #we write pulse sequences. for sector erase, the #data polling is valid after the last rising edge of the sector erase #we pulse. #data polling must be performed at sector addresses within any of the sectors being erased. otherwise, the status may not be valid. just prior to the completion of embedded algor ithm operations dq7 may change asynchronously while the output enable (#oe) is asserted low. this m eans that the device is dr iving status information on dq7 at one instant of time and then that byte s valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operations and dq7 has a valid data, the data outputs on dq0 ? dq6 may be still invalid. the valid data on dq0 ? dq7 will be read on the successive read attempts. the #data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or sector erase time-out (see "command definitions").
w39l040a publication release date: april 14, 2005 - 9 - revision a3 6.4.2 dq6: toggle bit the w39l040a also features the "toggle bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (#oe toggling) data from the device at any address will result in dq6 toggling between one and zero. once the embedded program or erase algorithm cycle is comp leted, dq6 will stop toggling and valid data will be read on the next successive attempt. during programming, the toggle bit is valid after the rising edge of the fourth #we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth #we pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase #we pulse. the toggle bit is active during the sector erase time-out. either #ce or #oe toggling will cause dq6 to toggle. 6.5 table of operating modes 6.5.1 device bus operations (v id = 12 0.5v) pin mode #ce #oe #we a0 a1 a9 dq0 ? dq7 read v il v il v ih a0 a1 a9 dout write v il v ih v il a0 a1 a9 din standby v ih x x x x x high z x v il x x x x high z/ dout write inhibit x x v ih x x x high z/ dout output disable v il v ih v ih x x x high z auto select manufacturers id v il v il v ih v il v il v id code auto select device id v il v il v ih v ih v il v id code 6.5.2 auto-select codes (high voltage method) (v id = 12 0.5v) description #ce #oe #we a9 the other address dq[7:0] manufacturer id: winbond v il v il v ih v id all address = v il dahex device id: w39 l040a v il v il v ih v id a1 = v ih , all other = v il d6hex
w39l040a - 10 - 6.5.3 sector address table sector a18 a17 a16 sector size (kbytes) address sa0 0 0 0 64 00000h ? 0ffffh sa1 0 0 1 64 10000h ? 1ffffh sa2 0 1 0 64 20000h ? 2ffffh sa3 0 1 1 64 30000h ? 3ffffh sa4 1 0 0 64 40000h ? 4ffffh sa5 1 0 1 64 50000h ? 5ffffh sa6 1 1 0 64 60000h ? 6ffffh sa7 1 1 1 64 70000h ? 7ffffh note: all sectors are 64k bytes in size. 6.5.4 command definitions command no. of 1st cycle 2nd cycle 3rd cy cle 4th cycle 5th cycle 6th cycle description cycles addr. (1 ) data a ddr. data a ddr. data a ddr. data a ddr. data addr. data read 1 a in d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3) 30 byte program 4 5555 aa 2aaa 55 5555 a0 a in d in product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 notes: 1. address format: a14 ? a0 (hex); data format: dq7 ? dq0 (hex) 2. either one of the two product id exit commands can be used. 3. sa: sector address sa = 7xxxxh for unique sector7 sa = 6xxxxh for unique sector6 sa = 5xxxxh for unique sector5 sa = 4xxxxh for unique sector4 sa = 3xxxxh for unique sector3 sa = 2xxxxh for unique sector2 sa = 1xxxxh for unique sector1 sa = 0xxxxh for unique sector0 4. xx: don't care
w39l040a publication release date: april 14, 2005 - 11 - revision a3 6.6 embedded programming algorithm start write program command sequence (see below) increment address programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit last address ? no yes program command sequence (address/command): pause t bp
w39l040a - 12 - 6.7 embedded erase algorithm start write erase command sequence (see below) erasure completed #data polling or toggle bit successfully completed 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h 5555h/10h chip erase command sequence (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h sector address/30h (address/command): individual sector erase command sequence pause t ec /t sec /t pec
w39l040a publication release date: april 14, 2005 - 13 - revision a3 6.8 embedded #data polling algorithm start read byte (dq0 - dq7) address = va pass dq7 = data ? yes no va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = any of the device addresses being erased during chip erase operation 6.9 embedded toggle bit algorithm start read byte (dq0 - dq7) address = don't care dq6 = toggle ? yes no pass
w39l040a - 14 - 7. electrical characteristics 7.1 absolute maximum ratings parameter rating unit operating temperature 0 to +70 c storage temperature -65 to +150 c power supply voltage to v ss potential -0.5 to v dd +0.5 v voltage on any pin to ground potential except a9 -0.5 to +4.0 v voltage on a9, #oe pin to ground potential -0.5 to +12.5 v note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. 7.2 dc operating characteristics (v dd = 3.0 ~ 3.6v for 70 ns or v dd = 2.7 ~ 3.6v for 90 ns, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply read current i dd1 #ce = v il , #oe = v ih , at f = 5 mhz - 7 12 ma power supply write current i dd2 #ce = v il , #oe = v ih - 15 30 ma standby v dd current i sb #ce = v dd 0.3v - 0.2 5 a input leakage current i li v in = v ss to v dd, v dd = v dd max. - - 1 a output leakage current i lo v out = v ss to v dd, v dd = v dd max. - - 1 a input low voltage v il - -0.5 - 0.8 v input high voltage v ih - 0.7 x v dd - v dd +0.3 v output low voltage v ol i ol = 4.0 ma, v dd = v dd min. - - 0.45 v v oh1 i oh = -2.0 ma, v dd = v dd min. 0.85 v dd - - v output high voltage v oh2 i oh = -100 a, v dd = v dd min. v dd -0.4 - - v 7.3 pin capacitance (v dd = 3.3v for 70 ns, or v dd = 3.0v for 90 ns, t a = 25 c, f = 1 mhz) parameter symbol conditions typ. max. unit input capacitance c in v in = 0v 6 7.5 pf output capacitance c out v out = 0v 8.5 12 pf
w39l040a publication release date: april 14, 2005 - 15 - revision a3 7.4 ac characteristics 7.4.1 ac test conditions parameter conditions input pulse levels 0v to 3.0v input rise/fall time <5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate c l = 30pf for 70ns/ 100pf for 90ns 7.4.2 ac test load and waveform +3.3v 1.2k 2.1k d out 30 pf for 70ns (including jig and scope) input 3v 0v test point test point 1.5v 1.5v output 100 pf for 90ns
w39l040a - 16 - ac characteristics, continued 7.4.3 read cycle timing parameters (v dd = 3.0 ~ 3.6v for 70 ns or v dd = 2.7 ~ 3.6v for 90 ns, v ss = 0v, t a = 0 to 70 c) 70 ns 90 ns parameter sym. min. max. min. max. unit read cycle time t rc 70 - 90 - ns chip enable access time t ce - 70 - 90 ns address access time t aa - 70 - 90 ns output enable access time t oe - 30 - 35 ns #ce high to high-z output t chz - 16 - 16 ns #oe high to high-z output t ohz - 16 - 16 ns output hold from address change t oh 0 - 0 - ns 7.4.4 erase/program cycle timing parameters 70 ns 90 ns parameter sym. min. typ. max. min. typ. max. unit write cycle time t wc 70 - - 90 - - ns address setup time t as 0 - - 0 - - ns address hold time t ah 45 - - 45 - - ns #ce setup time t cs 0 - - 0 - - ns #ce hold time t ch 0 - - 0 - - ns #oe setup time t oes 0 - - 0 - - ns #we pulse width t wp 35 - - 35 - - ns #we high width t wph 30 - - 30 - - ns data setup time t ds 35 - - 45 - - ns data hold time t dh 0 - - 0 - - ns byte programming time t bp - 9 200 - 9 200 s chip programming time t cp - 4.5 13.5 - 4.5 13.5 s chip erase cycle time t ec - 6 50 - 6 50 s sector erase cycle time t ep - 0.7 6 - 0.7 6 s note: all ac timing signals observe the following gui delines for determining setup and hold times: (a) high level signal's reference level is v ih and (b) low level signal's reference level is v il .
w39l040a publication release date: april 14, 2005 - 17 - revision a3 ac characteristics, continued 7.4.5 power-up timing parameter symbol typical unit power-up to read operation t pu . read 100 s power-up to write operation t pu . write 5 ms 7.4.6 #data polling and toggle bit timing parameters 70 ns 90 ns parameter sym. min. max. min. max. unit #oe to #data polling output delay t oep 10 - 10 - ns #ce to #data polling output delay t cep - 70 - 90 ns #oe to toggle bit output delay t oet 10 - 10 - ns #ce to toggle bit output delay t cet - 70 - 90 ns
w39l040a - 18 - 8. timing waveforms 8.1 read cycle timing diagram address a18-0 dq7-0 data valid data valid high-z #ce #oe #we t rc v ih t clz t olz t oe t ce t oh t aa t chz t ohz high-z 8.2 #we controlled command write cycle timing diagram address a18-0 dq7-0 data valid t as t cs t oes t ah t ch t oeh t wph t wp t ds t dh #ce #oe #we
w39l040a publication release date: april 14, 2005 - 19 - revision a3 timing waveforms, continued 8.3 #ce controlled command write cycle timing diagram high z data valid dq7-0 t as t ah t cph t oeh t dh t ds t cp t oes address a18-0 #ce #oe #we 8.4 chip erase timing diagram sb2 sb1 sb0 address a18-0 dq7-0 sb3 sb4 sb5 internal erase starts six-byte code for 3.3v-only software chip erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10 #ce #oe #we
w39l040a - 20 - timing waveforms, continued 8.5 sector erase timing diagram sb2 sb1 sb0 a ddress a18-0 dq7-0 sb3 sb4 sb5 internal erase starts six-byte commands for 3.3v-only sector erase t wp t wph t ep 5555 2aaa 5555 5555 2aaa sa aa 55 80 aa 55 30 sa = sector address #ce #oe #we 8.6 #data polling timing diagram address a18-0 dq7 x x x x t cep t oeh t oep t oes t ec t bp or an an an an #ce #oe #we
w39l040a publication release date: april 14, 2005 - 21 - revision a3 timing waveforms, continued 8.7 toggle bit timing diagram address a18-0 dq6 t oeh t oes t bp or t ec #ce #oe #we
w39l040a - 22 - 9. ordering information part no. access time (ns) power supply current max. (ma) standby v dd current max. ( a) package operatin g temp. ( c) cycle w39l040ap70b 70 12 5 32l plcc 0 ? 70 10k w39l040ap90b 90 12 5 32l plcc 0 ? 70 10k w39l040aq70b 70 12 5 32l stsop (8x14 mm) 0 ? 70 10k w39l040aq90b 90 12 5 32l stsop (8x14 mm) 0 ? 70 10k w39l040at70b 70 12 5 32l tsop (8 x 20 mm) 0 ? 70 10k w39l040at90b 90 12 5 32l tsop (8 x 20 mm) 0 ? 70 10k w39l040a70b 70 12 5 32l pdip 0 ? 70 10k W39L040A90B 90 12 5 32l pdip 0 ? 70 10k w39l040at70z 70 12 5 32l tsop (8 x 20 mm) lead free 0 ? 70 10k w39l040at90z 90 12 5 32l tsop (8 x 20 mm) lead free 0 ? 70 10k w39l040ap70z 70 12 5 32l plcc lead free 0 ? 70 10k w39l040ap90z 90 12 5 32l plcc lead free 0 ? 70 10k notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury mi ght occur as a consequence of product failure.
w39l040a publication release date: april 14, 2005 - 23 - revision a3 10. how to read the top marking example: the top marking of 32-pin tsop w39l040at-70 w39l040at70b 2138977a-a12 325obfa 1 st line: winbond logo 2 nd line: the part number: w39l040at70b 3 rd line: the lot number 4 th line: the tracking code: 325 o b sa 325: packages made in '03, week 25 o: assembly house id : a means ase, o means ose, ...etc. b: ic revision; a means version a, b means version b, ...etc. fa: process code
w39l040a - 24 - 11. package dimensions 11.1 32l plcc l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 notes: 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches. 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 11.2 32l pdip 1.dimensions d max. & s include mold flash or tie bar burrs. 2.dimension e1 does not include interlead flash. 3.dimensions d & e1 include mold mismatch an d are determined at the mold parting line. 6.general appearance spec. should be based on final visual inspection spec. . 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 01 5 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4.dimension b1 does not include dambar 5.controlling dimension: inches 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17
w39l040a publication release date: april 14, 2005 - 25 - revision a3 11.3 32l tsop (8 x 20 mm) a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d note: controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 11.4 32l stsop (8 x 14 mm) a a a 2 1 l l 1 y e h d d c min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 0.50 0.00 0 0.22 0.27 ----- 0.21 12.40 8.00 14.00 0.50 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.009 0.010 0.004 ----- 0.008 0.488 0.315 0.551 0.020 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm b e
w39l040a - 26 - 12. version history version date page description a1 sep. 24, 2004 - initial issued a2 nov. 25, 2004 3, 24, 25 added 32l pdip and 32l tsop package dimensions a3 april 14,2005 26 add important notice important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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